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PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) FEATURES * * * * * * * * * * 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100MHz - 200MHz. Complementary PECL outputs. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. High pull linearity: < 5%. +/- 120 ppm pull range Supports 2.5V or 3.3V-Power Supply. Available in 16-pinTSSOP and die form. Thickness 10 mil. DIE CONFIGURATION 57.5 mil BUFZSEL VDDOSC OSCOFF OESEL V GNDOSC VCON XIN 18 17 16 15 14 N/C (1460,1435) 13 12 VDDANA VDDBUF VDDBUF PECLBAR PECL GNDBUF 19 11 20 10 9 8 56.5 mil XOUT OECTRL 21 Die ID: 560A-EEEE-ER 7 22 1 2 3 4 5 6 GNDANA (0,0) DESCRIPTION PLL521-23 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. The chip provides a low phase noise, low jitter PECL differential clock output. X PACKAGE CONFIGURATION OUTPUT ENABLE LOGIC SELECTION OESEL* (Pad/Pin #14) 0 (Default) 1 OECTRL* (Pad #22, Pin # 6) 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled BLOCK DIAGRAM OE VCON Oscillator X+ XQ Q Amplifier w/ integrated varicaps * Bond to GND to set to "0", bond to VDD to set to "1". No connection results to "default" setting through internal pull-up/-down. Pad #22, Pin #6: Logical states defined by PECL VIH and VIL levels. HIGH IMPEDANCE BUFFER LOGIC SELECTION BUFZSEL (Pad/Pin #15) State Hi Z if Output is Disabled (Q=0) +(Qbar=1) if Output Disabled PLL521-23 0 (Default) 1 DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 56.5 x 57.5 mil GND 80 micron x 80 micron 10 mil 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 GNDBUF GNDBUF Y GNDOSC GNDANA VCON Rev 05/19/05 Page 1 PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) PAD ASSIGNMENT AND DESCRIPTION Die Pad Name Pad # VCON GNDOSC GNDANA GNDANA GNDBUF GNDBUF GNDBUF (optional) PECL PECLBAR VDDBUF (optional) VDDBUF 1 2 3 4 5 6 7 8 9 10 Description X (m) 329.6 498.3 696.2 825.0 973.6 1150.0 1183.6 1183.6 1183.6 1182.4 Y (m) 110.1 110.0 110.0 110.0 110.0 109.1 302.2 452.3 613.5 745.9 Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. GND connection for oscillator circuitry. GND connection for analog circuitry. GND connection for analog circuitry. GND connection for output buffer circuitry. GND connection for output buffer circuitry. GND connection for output buffer circuitry. PECL output PECL complementary output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. Do Not Connect Selector input to choose the OE control logic. See table on page 1. Output impedance selector VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. Oscillator Off Selection input pad. When low, turns off the oscillator when output is disabled. When high (default), oscillator running when output is disabled. Internal pull-up GND connection for oscillator circuitry. Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage (internally connected to pad 1). Crystal oscillator input pad. Crystal oscillator output pad. OE input pad. See table on page 1. 11 1252.4 903.6 VDDANA DNC OESEL BUFZSEL VDDOSC 12 13 14 15 16 1252.4 1058.5 864.5 624.0 467.1 1081.3 1221.6 1221.6 1222.6 1222.7 OSCOFF GNDOSC (optional) VCON XIN XOUT OECTRL 17 271.1 1222.6 18 19 20 21 22 109.4 108.9 109.0 108.6 108.6 1222.9 1062.1 865.8 358.4 146.5 Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/19/05 Page 2 PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) PACKAGE PIN ASSIGNMENT AND DESCRIPTION OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL 1 2 16 15 VDDOSC BUFZSEL OESEL VDDANA VDDBUF QBAR Q GND PLL521-23 3 4 5 6 7 8 14 13 12 11 10 9 DNC GND Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL DNC GND GND Q QBAR VDDBUF VDDANA OESEL BUFZSEL VDDOSC Description Oscillator Off Selection input pad. When low, turns off the oscillator when output is disabled. When high (default), oscillator running when output is disabled. Internal pull-up GND connection for oscillator circuitry. Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. Crystal oscillator input pin. Crystal oscillator output pin. OE input pad. See table on page 1. Do Not Connect. Ground connection. Ground connection. PECL Output. PECL complementary output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. Selector input to choose the OE control logic. See table on page 1. Output impedance selector VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/19/05 Page 3 PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature Input Static Discharge Voltage Protection SYMBOL VDD VI VO TS TA TJ MIN. VSS-0.5 VSS-0.5 -65 -45 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 2 UNITS V V V C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR SYMBOL FXIN CL (xtal) C0 C0/C1 (xtal) RE AT cut AT cut CONDITIONS Parallel Fundamental Mode Die at VCON = 1.65V MIN. 100 TYP. MAX. 200 UNITS MHz pF 5.0 3.5 350 30 pF 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON 3.3V, -3dB 2000 25 75 SYMBOL TVCXOSTB CONDITIONS From power valid XTAL C0/C1 < 350 0V VCON 3.3V at room temperature XTAL C0/C1 = 350 VCON = 0 to 3.3V MIN. 250 TYP. MAX. 10 UNITS ms ppm 120 3.3 - 8.8 5 ppm pF % ppm/V k kHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/19/05 Page 4 PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) 4. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Output valid after OE enabled Operating Voltage Output Clock Duty Cycle Short Circuit Current VDD @ Vdd - 1.3V (PECL) SYMBOL IDD CONDITIONS at 3.3V @ 155MHz Oscillator off Oscillator on MIN. TYP. 10 MAX. 55 UNITS mA ms V % mA 0.0001 2.25 45 50 50 3.63 55 5. Jitter specifications PARAMETERS Period jitter RMS at 155MHz Period jitter peak-to-peak at 155MHz Accumulated jitter RMS at 155MHz Accumulated jitter peak-to-peak at 155MHz Random Jitter Integrated jitter RMS at 155MHz Measured on Wavecrest SIA 3000 CONDITIONS At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz MIN. TYP. 2.0 15 2.0 20 2.0 0.25 MAX. 20 UNITS ps 25 ps ps 0.35 ps 6. Phase noise specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 155.52MHz 10Hz -70 100Hz -100 1kHz -130 10kHz -145 100kHz -145 1MHz -150 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/19/05 Page 5 PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) 7. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL V OH V OL CONDITIONS R L = 50 to (V DD - 2V) (see figure) MIN. V DD - 1.025 V DD - 1.620 MAX. UNITS V V 8. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time PECL Levels Test Circuit OUT VDD OUT SYMBOL tr tf CONDITIONS @20/80% - PECL @80/20% - PECL MIN. TYP. 0.6 0.6 MAX. 1.5 1.5 UNITS ns ns PECL Output Skew 50 2.0V 50% 50 OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/19/05 Page 6 PLL521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) ORDERING INFORMATION PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL521-23 PART NUMBER DC TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Order Number P521-23DC Marking P521-23DC Package Option Die - Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/19/05 Page 7 |
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